As the semiconductor industry advances, the search for smaller integrated circuit chips intensifies. This search includes many experiments concerning various structural configurations that utilize many different materials. Unfortunately, not all these experiments have been fruitful. For example, as the search for higher current devices has increased, so has the degree of failure in the integrated circuits due to structural meltdown and inadvertent electrical degradations. When the size of integrated circuits is decreased, there is a corresponding increase in channel hot-electron-induced degradation in transistors having a high voltage applied thereto.
Many devices have been successfully designed to work around the problem that has caused integrated circuits to have hot-electron-induced degradation at the gate. Despite the presence of these commonly reoccurring drain-to-gate shorts, there has been a lack of concentration on isolating these trouble areas on the integrated circuit board where shorts are more commonly located. In fact, prior art studies have been made to determine where physically "hot spots" are located on integrated circuit boards. If the integrated circuit were designed to minimize the circuitry located at these "hot spots", then the integrity of the integrated circuit could be served by limiting failure at these critical points on the integrated circuit chip.
The present invention recognizes the use of a polysilicon space formed adjacent to a gate of a transistor in conjunction with an oxide spacer formed on the polysilicon spacer transistor for increasing resistance to channel hot-electron-induced degradation.
Accordingly, there exists a need in the art for an arrangement which reduces degradation of circuitry on integrated circuit chips.